The deposition of tungsten (W) by chemical vapor deposition (CVD) enjoys wide application through various industries, particularly in manufacturing semiconductor devices. The escalating requirements for high device density and performance wiring require responsive changes, which is considered one of the most demanding aspects of ultra large scale integration (ULSI) technology. Such escalating requirements have been difficult to satisfy in terms of providing low resistance capacitance (RC) interconnect patterns, particularly wherein sub-micron vias, contacts and trenches have high aspect ratios due to miniaturization, e.g., greater than 3.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon, and a plurality of sequentially formed dielectric interlayers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, conductive patterns in different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines formed in trench openings typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor "chips" comprising 5 or more levels of metallization have become more prevalent as device geometries shrink into the deep sub-micron range.
A conductive plug filling a via hole is typically formed by depositing a dielectric interlayer on a conductive layer comprising as least one conductive pattern, forming an opening through the dielectric interlayer by conventional photolithographic and etching techniques, and filling the opening with conductive material. Excess conductive material on the surface of the dielectric interlayer is typically removed by chemical-mechanical polishing (CMP) or chemical etching.
In the formation of integrated circuit structures on and in a semiconductor wafer, one or more layers of metallization are employed to form conductive interconnects or wiring harnesses to various contacts on the processed wafer. Aluminum (Al) is conventionally employed in forming such wiring harnesses or patterned metal layers because it is relatively inexpensive, exhibits a relatively low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the deep sub-micron range, step coverage problems have arisen involving the use of Al, thereby decreasing the reliability of interconnections formed between different wiring layers. Such poor step coverage results in high current density and enhanced electromigration. Moreover, low dielectric constant polyamide materials, when employed as electric interlayers, create moisture/bias reliability problems when in contact with Al.
One approach to improved interconnection paths in vias comprises the use of W plugs. Accordingly, many current semiconductor devices utilizing high integration technology employ Al for a wiring metal and W plugs for interconnections at different levels.
However, the use of W is attendant with several disadvantages. For example, blanket deposition of a W layer on a semiconductor wafer is rather slow at a temperature of about 350.degree. C. Higher temperatures, e.g., about 500.degree. C. to about 550.degree. C., can be employed to increase deposition rates. However, such high temperatures render underlying portions of integrated circuit structures vulnerable to damage. Another disadvantage attendant upon depositing W is that the surface of the layer is not sufficiently uniform or smooth, resulting in a reflectivity of about 20% or less than that of a silicon substrate, thereby rendering it extremely difficult to conduct subsequent patterning of the deposited W layer by conventional photolithographic techniques. Another problem attendant upon depositing a layer of W is that the uniformity of the deposited layer may vary in an amount greater than 1% in thickness across the wafer, as measured by its resistivity.
In U.S. Pat. No. 5,028,565 issued to Chang et al., methodology is disclosed comprising introducing nitrogen (N.sub.2) during W CVD for improved surface reflectivity of the deposited W. N.sub.2 is also introduced during initial deposition of a nucleation layer, which nucleation layer is said to improve uniformity.
As the requirements for high density escalate, high uniformity, e.g., uniform thickness and as determined by resistivity measurement, of deposited W films becomes more significant and difficult to achieve both within a wafer and from wafer to wafer. Accordingly, there exists a need for methodology for depositing a W layer having improved uniformity. There also exists a need for methodology enabling the deposition of a W layer on a plurality of semiconductor wafers with high wafer-to-wafer uniformity.